In our day-to-day life the application of the electronic device plays a major role. As the technology develops the size of the devices are being decreased. It leads to wide usage of the FPGA devices and power consumption limits its application. The most of the electronic devices are battery operated devices. So power consumption is very essential criteria. The power consumption is based on static power and dynamic power. Static power consumption mainly depends on leakage power. The lookup table based fine grain power gating technique and effective utilization of logic block is used to reduce the leakage power. This technique is utilized to reduce the leakage power consumption in FPGA controlled device based on the concept of low power design and effective utilization of logic blocks.