In general, basic operations like addition, subtraction, and division may be performed using various types of binary adders in digitally based processors and control systems. The device's adder performance is solely used to measure a processor's or system's high speed and precision. Addition is one of the most vital and initial operations among all arithmetic operations and is utilized in many of the mathematical equations. In digital world, the addition operation can be performed by several adders. These adders produce carries with preferred power and delay. An adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Here an efficient adder circuit is implemented that revolves around reducing the cost to propagate the carry among consecutive bit positions. Hence in this work, design a high speed and area efficient KS (Kogge-Stone) and BK (Brent Kung) tree adder architecture. In this approach, the two Parallel Prefix Adders like Kogge-Stone and Brent Kung adders are used. This hybrid adder can significantly perform the addition operation with high speed and it requires less area.