The modern world is running forward in achieving the challenge of minimum area. So many efficient structures are employed in the traditional designs so that the max speed can be included. Most of the structures will have multiplier as the basic blocks , which will run with less speed because of its huge structure . in practical, not all applications need accurate results such as in image processing and digital signal processing etc. so approximate multipliers are employed. by considering these two points a scalable approximate multiplier, called truncation-and rounding-based scalable approximate multiplier (tosam)is presented, which reduces the number of partial products by truncating each of the input operands based on their leading one-bit position. In the proposed design, multiplication is performed by shift, add, and small fixed-width multiplication operations resulting in large improvements in the speed compared to those of the conventional multiplier. To improve the total accuracy, input operands of the multiplication part are rounded to the nearest odd number. Because input operands are truncated based on their leading one-bit positions, the accuracy becomes weakly dependent on the width of the input operands and the multiplier becomes scalable. higher improvements in design parameter (less area )is observed.