Approximate computing can decrease the design complexity with an increase in performance of area, delay and power efficiency for error resilient applications. This brief deals with a new design approach for approximation of multipliers. Approximate computing can decrease the design complexity with an increase in performance of area, delay and power efficiency for error resilient applications. This project proposes an accuracycontrollable multiplier whose final product is generated by a carry-maskable adder. The proposed scheme can dynamically select the length of the carry propagation to satisfy the accuracy requirements flexibly. The partial product tree of the multiplier is approximated by the proposed tree compressor. An multiplier design is implemented by employing the carry maskable adder and the compressor. Compared with a conventional multiplier, the proposed multiplier reduced power consumption. The implementation, synthesis and simulation is executed and noted in the Xilinx-ise in verilog hdl language.