The need for lower power Digital Signal Processing (DSP) devices has grown significantly as a result of the meteoric rise in mobile computing as well as portable multimedia applications. The most crucial factors in the construction of DSP systems and higher performance systems nowadays are low power consumption and small footprint. Finite Impulse Response (FIR) filters are among the most frequently utilized DSP techniques. In both signal processing and transmission, FIR filters are crucial. The main requirements for FIR filters are area minimization and speed. Operations including addition, multiplication, and shifting are used in FIR filters. The main building components of the filter are multipliers and adders, with multipliers taking up the most silicon space and using the most power. Digital circuits can use a variety of adders and multipliers, but constructing effective filters needs an effective adder and multiplier architecture. Thus, in this analysis, a PPA adder and multiplier are used to develop an effective VLSI architecture of a FIR filter. Reduced power units can be applied upon this multiplier and the design of full adders can be achieved; the outputs are then assessed for improved performance. Improved performance can be obtained with this FIR filter architecture in regards to latency, area, and overall power.