As the complexity and size of VLSI (Very Large-Scale Integration) designs tend to increase, pre-silicon fault detection technologies have become crucial for maintaining reliability in IC design. For the modern power system to be protected from transmission line faults, real-time monitoring and quick control are necessary. For power systems to operate with reliability, it is essential to identify and classify fault conditions. The engineers manual feature extraction having prior knowledge, which has been suggested by various scientists for fault detection and classification, is a key component of traditional fault diagnosis approaches. Any analog circuit's reliability depends heavily on the capacity to detect problems. By preventing potential severe damage from a defect, early fault detection can considerably aid in system maintenance. In the realm of fault detection and diagnosis, automatically and reliably recognizing the incipient micro-fault in power system, particularly for fault orientations as well as severity degree, remains a serious difficulty. Consequently, in this work, fault detection on the VLSI circuits employing R-FF design and implementation (Razor Flipflop). The Razor Flip-flop is a technology for circuit-level timing speculation that relies on dynamic failure and fault detection and correction in digital systems. The razor flip flop will increase the energy efficiency of presented system. This approach can effectively detect the faults in VLSI circuits.