[This article belongs to Volume - 54, Issue - 02]
Gongcheng Kexue Yu Jishu/Advanced Engineering Science
Journal ID : AES-31-07-2022-268

Title : Atspeed Scan Testing For Rtl Design In Lower Technology Node
Madhura.R, Dr Jamuna S

Abstract :

To achieve high yield and proper identification of damaged chips after production, a well-structured testing approach must be used. One way for detecting transition delay issues on system on chip is Atspeed scan testing. Atspeed patterns are applied to detect transition delay faults ,even though they stay for shorter duration .They are the cause for failures in the IC’s. In this paper, Atspeed patterns are applied for real time design under test to detect transition delay faults and able to achieve 71.85% fault coverage for stuck at type fault and 55% fault coverage for transition type fault through structural testing using 28nm technology using tessent tool. Different Fault classes like DS, DI AU are also found out for total number of faults. Fault Simulation is done for the intended design to find the faults from fault list for the deterministic test patterns using Launch on capture method.