Numerical impulse response Wireless sensor networks (WSNs) and signal processing both frequently use FIR filters. The multipliers used in the design of FIR filter topologies are notoriously space-hogs. When putting together complicated algorithms, FIR filter design relies heavily on performance aspects like hardware cost and area. Three different kinds of adders—the Kogge stone adder, the sklansky adder, and the square root carry select adder—were chosen for this task. This paper's objectives include being familiar with the XILINX synthesizer, creating an RTL for the constructions, and confirming the structures' capacity to perform the desired functions. Different types of FIR trees are compared to one another in terms of pace. In this paper, the VERILOG programming language to create a FIR filter in XILINX ISE is being used. VERILOG is used to write the code for the FIR filter in this paper, and waveform simulation is used so that the results may be analyzed.