This Project describes a one-sided Schmitt-triggered with data independent read and write operation from a 9T Static Random-Access Memory (SRAM) cell that consume less power and has excellent read and write stability. The existing approaches are performed with data leakage problem, huge area, expensive energy per access read data bits. To solve this problem, the proposed work will introduce three duplications of Static RAM cells with read ports to arise ST 12T SRAM, with the goal of greatly reducing data based read port leakage to improve the read quality and minimize area and power. The proposed methodology of Schmitt trigger based 12T SRAM memory cell achieves excellent read robustness in a one-sided Schmitt-triggered inverter with a three different single bit arrangement, while the write ability improves by power gating in Schmitt-trigger-inverter with support of control and trip voltage. This article’s proposed approach 12T SRAM memory cell will be designed at the single bit level, utilizing 16 nm CMOS Technology, and demonstrate the area, latency and power consumption using Mentor Tanner EDA Tool.