The increasing complexity of the DSP systems demanding higher computational performance in its architecture. But the traditional DSP arithmetic has limits in terms of speed of calculations. More over in some applications speed is more important than accuracy. In order to further enhance performance, approximate arithmetic circuits are designed with some loss of accuracy to reduce energy consumption and increase the speed. These approximate circuits have been considered for error-tolerant applications. In this paper, we propose an FIR filter based on Rounding Based Approximate (ROBA) Multiplier. In this multiplier the operands are rounded to the nearest exponent of two. This approximation will lead to simplification of multiplication operation thus reducing area and increasing speed. As the multiplier is the slowest element in the system, it will affect the performance of the overall FIR filter. The proposed ROBA multiplier based FIR filter was compared with HAAM and DRUM multiplier based FIR filters. The results shown significant reduction in the power and area of the FIR filter with proportional improvement in the multiplier speed. The Filter was implemented and tested using Virtex 5 FPGA at an operating voltage of 1.0V using Xilinx ISE environment.