The increasing demand for energy-efficient and high-performance digital systems has made the design of low-power arithmetic circuits a critical area of research. Full adders, being core components of arithmetic logic units (ALUs), play a vital role in determining the overall efficiency of digital architectures. This paper presents a novel Low-Power Hybrid 4-bit Full Adder design utilizing 14nm FinFET technology to address the challenges of power consumption and speed in modern computing applications. The proposed architecture combines Gate Diffusion Input (GDI) logic with Energy-Efficient Diode-Connected DC Biased Positive Feedback Adiabatic Logic (EE-DC-DB PFAL), leveraging both logic minimization and adiabatic switching to enhance power performance. FinFET devices are employed to exploit their superior electrostatic control and reduced leakage characteristics at the nanoscale. Comprehensive simulations conducted using industry-standard tools demonstrate significant improvements in power dissipation, delay, and energy efficiency compared to traditional CMOS-based full adder designs. The results validate the effectiveness of the proposed hybrid approach, making it a promising candidate for integration into low-power digital processing units and future ultra-scaled VLSI systems.