[This article belongs to Volume - 55, Issue - 02, 2023]
Gongcheng Kexue Yu Jishu/Advanced Engineering Science
Journal ID : AES-06-09-2023-11

1P.Syed Anjum Thaslim,2Dr.M.V.Subramanyam,3N.Sreenivas Rao,4K.Pedda obulesu,5M.Mahesh Kumar, 6K.Vinod Kumar,6N.Jyothsna,

Abstract :

One of the most often used mathematical procedures is multiplication. usage of mathematics in fields as disparate as computational brain networks and audio processing. One of the main forces at work in such contexts is the multiplier. energy consumption, critical path delay, and resource use. In FPGA-based systems, the intensity of these effects tends to grow. However, most state-of-the-art ideas have been previously made for ASIC-based systems. A few FPGA-based systems that can only handle undocumented integers, requiring extra circuitry for verified operations. In order to overcome these restrictions for FPGA-based applications, This research supplies an increase that balances low latency or energy efficiency using a signed-number-based exact signing scheme that achieves optimal area utilization. Vivado's area-optimized multiplier is used as a comparison. Our IP deployments may deliver 40%, forty per cent, and 70% savings, respectively.